一款Verilog模拟器，用于 ASIC 和 FPGA设计的确认.

LogicSim 3.3 - Stop Bugs Ruining Your Day
Today automated design verification plays a vital role in many ASIC and FPGA projects. Automated verification has long been thought critical for large IC development organizations, but is often considered to be too expensive and difficult to implement for smaller companies. Zeemz's LogicSim breaks this stereotype.

LogicSim is an affordable and user-friendly Verilog simulator for ASIC and FPGA design verification. It delivers a powerful and easy-to-use graphical user interface that lets you quickly simulate your Verilog designs. It's built on our state-of-the-art single kernel simulation engine MULCORED™ (Multi-Core Event Distribution) technology.

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